The logic circuit simulator is an important component of any computer-aided design (CAD) system for digital circuits. It is used to predict logic circuit operation and performance under normal and faulty conditions. Applications of logic circuit simulators can be divided into two major area--the verification of new logic hardware designs and the analysis of the behavior of these designs under faults.
The circuit to be analyzed is modeled on a logic circuit simulator using a circuit description language. This language describes the connectivity and behavior of the circuit. The modeling information typically includes element type (gate or functional), associated delays, and interconnection data. The computer model is then compiled into a predefined data structure and simulated inputs are applied either dynamically (at prescribed times) or statically (after the circuit is stabilized). If fault simulation is being performed, faults are inserted in the model. The simulated output is recorded either in plot form, for fault-free simulation, or tabular form, for fault simulation.
Currently, most digital circuits are simulated on large general-purpose computers. While this approach is satisfactory for up to many thousands of gates, its applicability to very large scale integrated (VLSI) circuits is doubtful, at least in the manner that it is currently used. Very large simulation times and costs result when dealing with circuits of VLSI complexity (more than about 100,000 gates on a single chip). There is a definite need for more sophisticated and cost-effective simulators in the VLSI era.
Existing logic circuit simulators are implemented in software which is executed on a general purpose computer. To date, a large amount of work has been invested in optimizing this software, by improved data structures and more efficient algorithms. But the capacity of the existing software-based simulators is becoming exhausted as VLSI-complexity circuits are being designed. The wider use of VLSI devices will largely depend on the future availability of lower-cost simulators that run at high speeds. However, the speed improvements required for efficient VLSI design cannot be obtained by using faster processors. One way to obtain further improvements in the performance of the logic circuit simulators is to optimize the hardware on which the simulation software executes. With the advent of low cost microcomputers, the development of special purpose logic simulation hardware becomes attractive. Possible benefits are higher speeds, lower costs, and greater flexibility (for example, better integration in a test station).
The architecture of a special purpose logic simulation machine for true value simulation and fault simulation has been developed and described. See, for example, Y. H. Levendel, P. R. Menon, and S. H. Patel, "Special Purpose Logic Simulator Using Distributed Processing," Bell System Technical Journal, (B.S.T.J.) Vol. 61, No. 10 (December 1982), pp. 2873-2909, and Y. H. Levendel, P. R. Menon, and S. H. Patel, "Parallel Fault Simulation Using Distributed Processing," B.S.T.J., Vol. 62, No. 10 (December 1983), pp. 3107-3137. The system described there is essentially a parallel-processing network based on an interconnection of 1ow-cost microcomputers. The circuit to be simulated is partitioned into subcircuits and each subcircuit in simulated in a separate microcomputer, referred to as a slave processor. The modularity of the proposed simulator allows easy increase of computational power.
For a given fixed number of processors, however, the speed of the multiprocessor-based simulator is limited by the execution time of the slave processors. To, obtain further speed improvements, the slave processors must be able to execute the simulation process faster. In particular, it is estimated that in deductive fault simulation, which is an efficient method of simulating a large number of faults, up to 80% or more of the processing time is spent in computation of fault lists and in movement of fault lists between a slave processor and its input/output buffers. The time required for these operations therefore needs to be reduced.